Data processing systems which selectively write bytes in a multibyte memory word location in a memory system are known in the art. An example of such a system is described in U.S. Pat. No. 4,045,781. This patent teaches the use of control signals and the least significant two bits of the address for the selective writing of bytes within a memory word location addressed by the remaining bits of the address. The patent further teaches that these signals may be decoded and transmitted by a write decoder to the memory system with parity bits to allow the detection of errors caused by a malfunction of the memory system. The consequences of a wrong byte being written and going undetected is of serious consequence to data processing systems. In a data processing system which requires high reliability, it is necessary to be able to detect any occurrence of the wrong byte being written. However, the prior art does not teach a method for detecting errors in either the transmission path or the write decoder. Further, the prior art does not teach a method for detecting a memory system malfunction which causes the writing of an unselected byte.